With the advent of Ultra Large Scale Integrated (ULSI) circuits technologies, it has been a trend to scale down the geometry dimension of semiconductor devices and increase the density of semiconductor devices per unit area of silicon wafer. Electro-static discharge (ESD) protection is one of the important issues in the design of integrated circuits. ESD is also a significant problem of the fabrication of integrated circuits. For example, various transient sources such as human or machine handling of the semiconductor wafer or chip during assembly, processing. These will cause destructive electro-static pulses.
Developments in the formation of sub-micron semiconductor technologies have been quite modest in comparison. The renewed interest in high density hybrids is driven by the requirement to handle large numbers of IC interconnections, the increasing clock rate of digital systems and the desire to pack greater functionality into smaller spaces. Thus, the thickness of the gate oxide, and the length of the device's channel have become thinner or shorter than ever. The failure susceptibility of integrated circuits to ESD protection increases due to the IC fabrication towards sub-micron feature lengths.
Typically, input/output signals to a complimentary metal oxide semiconductor (CMOS) device are connected to input/output pads. The input/output pads are generally connected to the gates of metal oxide semiconductor (MOS) devices. All pins for input/output of MOS IC must be ESD protected to prevent harmful static discharge voltages from damaging the IC. In order to increase clock rate of digital systems, the number of the pins is increased in the IC. Subsequently, the available area for forming the guard ring is limited.
As shown in FIG. 1, it shows a conventional layout of ESD protection for a MOS service. The structure includes a plurality of finger structures 100 to serve as gate structures. The drain region 110, source regions 120 are formed between the gate structures 100. The gates 100, the sources 120 and drains 110 construct MOS devices. A ring area 130 having p+ doped ions surrounds the MOS devices and is connected to ground. Another ring area 140 keeps a distance from the ring area 130 and surrounds the ring area 130 for serving as a guard ring for the MOS device. Typically, the ring area 140 is doped with n+ doped ions. The current distribution of the gates is not uniform due to the MOS having LDD structure. The equivalent circuit of the prior art includes multi-bioplars. The current distribution in each bipolar is different due to each bipolar with different substrate-resistor. Thus, the ESD damage site is located at the region near P-substrate pick-up due to current crowing there.
Turning to FIG. 2, the structure includes a plurality of rectangular ring structures 200 to act as gates. Drains 210 are formed inside the rectangular ring structure 200. An area 220 outside the rectangular ring structure 200 is source. A ring structure 230 is adjacent to the area 220 and surrounds the area 220. The doped ions of the ring structure 230 is p+ impurities and connected to ground. An n+ doped region 240 is separated from the ring structure 230 with a distance to act a guard ring. The bias of the n+ doped region 240 is Vcc. Further, the ring structure 230 is surrounded by the n+ doped region 240.
A plurality of drain contacts 250 is located in the areas 210. A plurality of contacts 260 is formed in the ring structure 230 for electrical contact. The source 220 includes a plurality of source contacts 270 formed along the gate structures 200. In addition, the source contacts 270A between the neighboring gate structures 200 is shared by the two neighboring gate structures 200. FIG. 3 is a equivalent circuits drawing according to the FIG. 2, and the cross section view taken from the A-A' line of FIG. 2 is shown in FIG. 4. By analysis of the circuits, the layout of the aforementioned causes the current to accumulate at the p+ doped region 230, thus the current distribution is not uniform in the prior art. This will degrade the capability of ESD protection.
What is required is a layout structure to upgrade the carriers distribution uniform in the ESD protection circuits.